A novel power-efficient reconfigurable mode converter is proposed and experimentally demonstrated based on cross-connected symmetric Y-junctions assisted by thermo-optic phase shifters on a silicon-on-insulator platform. Instead of using conventional Y-junctions, subwavelength symmetric Y-junctions are utilized to enhance the mode splitting ability. The reconfigurable functionality can be realized by controlling the induced phase differences. Benefited from the cross-connected scheme, the number of heating electrodes can be effectively reduced, while the performance of the device is maintained. With only one-step etching, our fabricated device shows the average insertion losses and cross talks are less than 2.45 and -16.6dB, respectively, measured with conversions between two arbitrary compositions of the first four TE modes over an observable 60 nm bandwidth. The converter is switchable and CMOS-compatible, and could be extended for more modes; hence, it can be potentially deployed for advanced and flexible mode multiplexing optical networks-on-chip.

A high-efficiency inverse design of “digital” subwavelength nanophotonic devices using the adjoint method is proposed. We design a single-mode 3 dB power divider and a dual-mode demultiplexer to demonstrate the efficiency of the proposed inverse design approach, called the digitized adjoint method, for single- and dual-object optimization, respectively. The optimization comprises three stages: 1) continuous variation for an “analog” pattern; 2) forced permittivity biasing for a “quasi-digital” pattern; and 3) a multilevel digital pattern. Compared with the conventional brute-force method, the proposed method can improve design efficiency by about five times, and the performance optimization can reach approximately the same level. The method takes advantages of adjoint sensitivity analysis and digital subwavelength structure and creates a new way for the efficient and high-performance design of compact digital subwavelength nanophotonic devices, which could overcome the efficiency bottleneck of the brute-force method, which is restricted by the number of pixels of a digital pattern, and improve the device performance by extending a conventional binary pattern to a multilevel one.